Metal traces and through silicon vias (TSVs) are used to connect with the stacks each other in a stacked integrated circuit (IC). When a charged-device model (CDM) electrostatic discharge (ESD) event occurs on the stacked IC, accumulated charge in each stack will be discharged via the TSVs and the metal traces of each stack in the stacked IC. However, accumulated charge in each stack may be easily liable to generate an excessive current due to simultaneous discharge when the CDM ESD event occurs on the stacked IC.
FIG. 1 illustrates schematic waveforms of electrostatic discharge currents in a stacked integrated circuit. As shown in FIG. 1, waveform 11 represents a discharge current of accumulated charge in a stack of the stacked IC, while waveform 13 represents a total discharge current which is a sum of discharge currents discharging substantially at the same time from stacks of the stacked IC.
During a CDM ESD event, accumulated charge may be discharged in a discharge current at a certain time point, with a considerably high current peak in a relatively short period.
The damage caused by CDM ESD to components of an input/output circuit could be reduced by providing CDM ESD protection for a stacked IC.